Constant divider

ABSTRACT

A constant divider is described which includes: a plurality of stages of partial dividers each including a group of decoders, one decoder being provided for each bit of a dividend and each decoder outputting a quotient and remainder resulting from division of a value associated with a bit when that bit is &#34;1&#34;, and quotient adders that add the quotient output of each decoder of that decoder group; in partial dividers other than that of the last stage, a remainder adder that adds output values of remainders of each decoder of the decoder group of that stage; in the last stage of the partial dividers, a corrective decoder that outputs a corrective output of the quotient and a corrective output of the remainder produced by dividing the output of the remainders of each decoder of the last-stage decoder group by the divisor; and finally, a quotient output adder that adds the quotient adder output of each stage and the corrective output of the quotient of the last stage, wherein the first-stage partial divider receives the dividend, partial dividers of succeeding stages receive as the dividend the output of the remainder adder of the partial divider of the preceding stage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a divider, and particularly to theconfiguration of a divider in which the divisor is a fixed constant.

2. Description of the Related Art

The circuit configuration of dividers known in the prior art that areconstructed from, for example, integrated circuits take as a basis asubtraction process in which the quotient is the number of times thedivisor can be subtracted from the dividend and the balance is theremainder. Devices taking the subtraction process as a basis adopt avariety of methods of accelerating the processing speed. The number ofsubtractions is reduced by repeatedly obtaining the remainder (partialremainder) and the quotient (partial quotient) by subtracting thedivisor from the higher-order digit of the dividend and then obtainingthe quotient and remainder of the next column by again subtracting thedivisor from the sum of this remainder and the succeeding digit.

The number of processes can be further reduced in cases in which thedivisor is a pre-determined constant. For example, Japanese PatentLaid-open No. 88334/86 describes a case in which the quotient andremainder are stored in a memory for a figures assumed in advance to bedividends, following which the memory is addressed by the dividend toextract the quotient and remainder. However, a massive amount of memoryis required if the figures presupposed as the dividend are set toinfinity, and consequently, the quotient and remainder for all numbersof a set digit number are set in memory, the memory is addressed fromthe higher-order digits of the dividend and partial quotients andpartial remainders obtained, and the same processes repeated for numbersresulting from addition of these partial remainders to obtain the finalquotient and remainder.

A large number of division processes are thus required if a divisionprocess is repeated. For example, a processing time of at least onecontrol clock is required for each division process, and the processingtime increases in accordance with the number of digits or the number ofbits of the dividend. This problem will be further explained withreference to the accompanying figures.

FIG. 1 is a block diagram showing the divider described in JapanesePatent Laid-open No. 88334/86, FIG. 2A is a flowchart of the processesof this divider, and FIGS. 2B and 2C are flowcharts showing the state ofthe operation register. As shown in FIG. 1, the dividend is sent by wayof line 500 and is then set to operation register 504 under the controlof selector 506. The higher-order bit information of the dividend storedin operation register 504 passes by way of line 503 and is applied todivision memory 505 as an address, and a partial remainder and partialquotient are each outputted to line 501 and line 502, respectively. Thepartial remainder of line 501, together with the lower-order bitinformation of the dividend that has not undergone the operation processthat is supplied from line 507, are again set to operation register 504by way of selector 506. The higher-order bit information that is thusset again to operation register 504 is subjected to the division processusing division memory 505, and a similar division process is repeateduntil the value within operation register 504 is less than the divisor.

An explanation will next be presented using FIG. 1 and FIGS. 2A-2C whichillustrate a concrete operation in which the 3 higher-order bits fromoperation register 504 are taken as the object of the division process,the binary number value of dividend being "1111b" and the binary numbervalue of the divisor being "10b" (b indicating that these are binarynumbers). In the first subtraction process loop, the 3 higher-order bitsof dividend "1111b" set to operation register 504 (i.e., "111b") areapplied to division memory 505 as an address by way of line 503. Thevalues for the partial quotient "11b" and partial remainder "1b" are setin advance at address "111b" and are outputted from lines 501 and 502.Partial quotient, partial remainder, and the remaining bits of dividendare reset to operation register 504 by means of selector 506 and valueobtained. The partial quotient "11b" outputted by way of line 502 is setto the lower-order bit 601 of operation register 504. The partialremainder "1b" outputted by way of line 501 is set to the higher-orderbit 602 of operation register 504. The remaining bits of the dividendare set between the partial quotient and partial remainder following thepartial quotient. The value of operation register 504 is thus "1111b" asa result of the first division process loop. Next, the higher-order bit"11b" made up by the partial remainder "1b" and the remaining bit "1b"of the dividend is still greater than the divisor "10b", and this valueis therefore added to division memory 505 as an address by way of line503, and the second division process loop is carried out. The partialquotient "1b" and partial remainder "1b" are set at address "11b" ofdivision memory 505. The partial quotient "1b" is set to the lower-orderbit 603 of operation register 504, the partial remainder "1b" is set tothe higher-order bit 604, and the first partial quotient "11b" isshifted to the higher order of lower-order bit 603. As a result, thehigher-order bit "1b" apart from partial quotients 605 and 603 becomessmaller than the divisor "10b", thereby completing the division process,and the value "111b", which is the combination of partial quotients 605and 603, is taken as the final quotient, and the last remainder "1b" istaken as the final remainder.

The division process is thus repeated a plurality of times despite theuse of memory and division cannot be realized in a single process, whichis the minimum number of processes, and the processing time isprotracted. Reducing the number of bits taken from operation register504 and used to address the division memory decreases the amount ofmemory required, but also increases the number of loops of divisionprocessing and lengthens the processing time. On the other hand,increasing the number of bits used to address the division memoryshortens the processing time but increases the amount of memory requiredby an exponent of the number of bits.

Japanese Patent Laid-open No. 190928/90 discloses an example in which acomparator circuit and a decoder are used in place of the memory that isused in the above-described example of the prior art. This devicereplaces division memory 505 of FIG. 1 with a divider that employs acomparator circuit and decoder, provides a plurality of comparatorcircuits that compare an integer power of the divisor with the bits tobe divided of the dividend, calculates partial quotients and partialremainders by decoding the output of this plurality of comparatorcircuits at the decoder, and in the same way as the prior-art example ofFIG. 1, takes the combination of partial quotients as the final quotientand the last remainder as the final remainder.

As with the prior-art example employing a memory (Japanese PatentLaid-open No. 88334/86), this example of the prior art entails aplurality of division processes and a protracted processing time.Moreover, as in the other prior-art example that uses a memory, thenumber of comparator circuits in this example increases with the numberof bits of the object division for which partial quotients are produced,but this example raises an additional problem in that comparatorcircuits require far more space than a case using memory.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a divider in which thedivisor is fixed and that requires a shorter processing time.

Another object of the present invention is to provide a divider in whichthe divisor is fixed and that can decrease processing time by notincluding process loops in which the same process is repeated within theprocess flow.

Still another object of the present invention is to provide a divider inwhich the divisor is fixed, that has a configuration suited to asemiconductor integrated circuit, and in which, despite the improvementin processing speed, the surface area on the integrated circuit that ismonopolized by the circuit structure necessary for the division processis small.

A divider according to the present invention comprises:

in a divider that divides a dividend by divisor that is a predeterminednumber;

a decoder group composed of decoders that receive a dividend, that areprovided for each bit of the binary number of this dividend, and that,when the bit is "1b", output a quotient and a remainder produced bydividing a value held by the bit by the divisor; and, when that bit is"0b", output "0" as the quotient and the remainder;

a quotient adder that adds the value of the quotients outputted by eachdecoder of the decoder group; and

a remainder adder that adds the value of the remainder outputted by eachdecoder of the decoder group.

In addition, a divider according to the present invention comprises:

a plurality of stages of partial dividers that divide a dividend by adivisor which is a predetermined number and that each include: a decodergroup composed of decoders that receive a dividend, that are providedfor each bit of the binary number of this dividend, and that, when thebit is "1b", output a quotient and a remainder produced by dividing avalue held by the bit by the divisor; and when that bit is "0b", output"0b" as the quotient and the remainder; and a quotient adder that addsthe value of quotients outputted by each decoder of this decoder group;

remainder adders in the partial dividers other than that of the laststage that add values of the remainders outputted by each decoder of thedecoder group of that stage;

a corrective decoder in the partial divider of the last stage thatoutputs a corrected output of a quotient and a corrected output of aremainder produced by dividing by the divisor the output value of theremainder of each decoder of the decoder group of the last stage;

a quotient output adder which adds the outputs of the quotient adders ofeach stage and the corrected output of the quotient of the last stage,wherein the partial divider of the first stage receives the dividend andthe partial dividers of each succeeding stage receive as dividend theoutput from the remainder adder of the partial divider of the precedingstage; whereby the output of this quotient output adder is taken as thefinal quotient and the corrected remainder output from the correctivedecoder of the partial divider of the last stage is taken as the finalremainder.

Moreover, a method of dividing by a constant according to the presentinvention comprises, in a method in which a dividend is divided by apredetermined divisor:

a decoding step in which a dividend is received, and for each bit of thebinary number of this dividend, a quotient and remainder produced bydividing the value held by the bit by a divisor are outputted when thebit is "1b", and "0" is outputted as the quotient and remainder when thebit is "0b";

a quotient adding step in which the quotients outputted for every bit inthe decoding step are added;

and a remainder adding step in which the remainders outputted for everybit in the decoding step are added.

In addition, the method of dividing by a constant according to thepresent invention is a method which effects division by a divisor whichis a predetermined number, which executes a plurality of division stepsincluding: a decoding step in which a dividend is received, and for eachbit of the binary number of this dividend, a quotient and remainderproduced by dividing a value held by a bit by a divisor are outputtedwhen the bit is "1b", and "0" is outputted as quotient and remainderwhen the bit is "0b"; and a quotient adding step in which quotientsoutputted for every bit in the decoding step are added;

the method comprising:

in the plurality of division steps other than the last division step,remainder adding steps in which the remainders outputted for each bitare added;

a corrective decoding step in which a corrective output of the quotientand corrected output of a remainder produced by dividing by a divisor aremainder outputted for every bit are outputted in the last divisionstep of a plurality of division steps; and

a quotient output adding step in which, in the first division step, thedividend of the sought division is received as the dividend and insucceeding division steps the output of the remainder adding step of thepreceding division step is received as the dividend, and the output ofeach quotient adding step and the corrective output of the quotient ofthe last division step are added;

the output of this quotient output adding step being taken as the finalquotient, and the corrected remainder output of the corrective decoderstep of the last division step being taken as the final remainder.

According to the present invention, loops in which processes arerepeated are eliminated because the decoders are used in a series, andthe division process therefore does not require control by a clock. As aresult, a division process can be completed in one clock, therebyallowing an increase in processing speed. Consequently, complex timingneed not be considered when designing a circuit, and circuit design isaccordingly simplified. Moreover, decoders are formed according to thebit units of the dividend, and the circuit configuration of each decoderis therefore automatically determined when the divisor is established.In the examples of the prior art in which division must be repeated forthe plurality of bits of the dividend, difficulty is encountered inattempting to accelerate the processing speed or restrain increases insize due to space requirements of memory or comparators. In contrast,the decoders used in this invention are much smaller than comparators,and moreover, do not require space-consuming peripheral devices such asaddress control or sense amplifiers as would a memory in a prior artcase. The present invention therefore enables high-speed divisionwithout monopolizing a large area.

The above and other objects, features, and advantages of the presentinvention will become apparent from the following description based onthe accompanying drawings which illustrate examples of preferredembodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a constant divider using a memoryaccording to the prior art.

FIG. 2A is a flowchart of the process of a constant divider using amemory according to the prior art.

FIG. 2B is an explanatory view of the operation of a constant dividerusing a memory according to the prior art.

FIG. 2C is an explanatory view of the operation of a constant dividerusing a memory according to the prior art.

FIG. 3 is a block diagram showing the configuration of a firstembodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a secondembodiment of the present invention.

FIG. 5 is a flowchart showing the process by the second embodiment ofthe present invention.

FIG. 6 is a block diagram showing the construction of a third embodimentof the present invention.

FIG. 7 is a flowchart showing the process of the third embodiment of thepresent invention.

FIG. 8 is a table for explaining the operation of the decoder of eachembodiment of the present invention.

FIG. 9 is a timing chart for illustrating the operation of eachembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will next be explained with reference to theaccompanying figures.

FIG. 3 is a block diagram showing the first embodiment of the presentinvention. This embodiment uses a decoder made up of just one stage, andthe dividend is brought to decoder 1 by way of line 101. Decoder 1 is ageneral name for the entire component, and in actuality, an individualdecoder is provided for each bit of the 64 bits which constitute themaximum number of bits in a dividend, and each bit of the dividend,which is received as a binary number, is inputted to a correspondingindividual decoder.

The individual decoders are designed so as to decode the state when anumber corresponding to arranged bits is divided by a pre-set divisor.In other words, the individual decoders are designed so as to output "0"as the quotient and remainder when the bit information of the dividendheld by that bit is "0b", and to output the quotient and remainderproduced by dividing the decimal number value held by the bit by thepreset divisor when the dividend bit information held by the bit is"1b". For example, when the dividend is the binary number "1111b" andthe divisor is "10b", the decoder of the least significant bit outputs"0" as the quotient and outputs the decimal number value of the dividendof that bit as the remainder (in this case, "1h" (where h indicates thatthe number is a decimal number)). Since the bit of the dividendcorresponding to the second bit from the least significant bit is "1b",the decoder of this bit is designed so as to output "1h" as the quotientand to output "0" as the remainder. Since the bit of the dividendcorresponding to the third bit from the least significant bit is "1b",the decoder of this bit is designed to output "2h" as the quotient and"0" as the remainder. In the same way, the decoder of the mostsignificant bit is designed to output "4h" as the quotient and "0" asthe remainder.

The quotient output of each individual decoder is sent from line 106(provided in a number equal to that of the individual decoders) toaddition circuit (adder) 4 and added. The remainder output of eachindividual decoder is sent by line 105 (provided in a number equal tothat of the individual decoders) to corrective decoder 10 where it isdetermined by decoding processing whether or not the remainder is largerthan the divisor. If the remainder is greater than the divisor, acorrective output of the quotient is outputted to the addition circuit.The final remainder is outputted by corrective decoder 10. The exampledescribed in the explanation of the construction of individual decodershas no corrective output for the quotient, and the output of quotientadder 4 is therefore "1h"+"2h"+"4h"="7h", and the output from thecorrective decoder 10 is "1h". These outputs are the final quotient andremainder.

Regarding the role of corrective decoder 10, if the value of the divisoris of 4 bits (for example, "1100b"), no quotient will be outputted forthe lower 4 bits of the dividend because each bit is divided by thedivisor, and as a result, a remainder greater than the divisor isgenerated. The value of the final quotient is corrected by decoding thisremainder, which is greater than the divisor.

The second embodiment is formed by a two-stage decoder having a circuitconfiguration shown in the circuit block diagram in FIG. 4 and adivision process illustrated in the flowchart of FIG. 5.

The dividend is inputted to first-stage decoder 1 from line 101.Decoders 1 are provided for each bit of the dividend, and at each bit,if the bit of the dividend is "1b", the quotient produced by dividingthe numerical value of that bit by the divisor is outputted to line 106and the remainder is outputted to line 105. The quotient output of eachdecoder 1 is added at addition circuit 4. The remainders are similarlyadded at addition circuit 5. The addition value of each remainder (theoutput of addition circuit 5) is applied to second-stage decoder 2.Second-stage decoders 2 are also provided for each bit of the binarynumber of the addition circuits, and if a bit is "1b" the quotientproduced by dividing the numerical value of that bit by the divisor isapplied to addition circuit 6 by way of line 109. The remainders areapplied to corrective decoder 10 by way of line 108. No output isproduced if the bit of a second-stage decoder 2 is "0b". The remaindersfrom a plurality of second-stage decoders 2 are added to correctivedecoder 10, a corrective value of the quotient is outputted to additioncircuit 9 if the sum of the remainders is greater than the divisor, andthe balance is outputted to line 110 as the final remainder. If the sumof remainders from the plurality of second-stage decoders 2 is less thanthe divisor, no corrective value of the quotient is generated and theremainder is outputted from line 110 without alteration. On the otherhand, the output of addition circuit 4 and the output of additioncircuit 6 are applied to addition circuit 9 together with the correctivevalue of the quotient of corrective decoder 10, and outputted as a finalvalue to line 103.

The third embodiment of the present invention is formed from a decoderof three-stage construction having a circuit configuration shown by theblock diagram of FIG. 6 and a division process shown by the flow chartof FIG. 7.

Each binary number bit of the dividend is applied to first-stage decoder1 by way of line 101. Decoding for division by the divisor is performedfor each bit by first-stage decoder 1, the quotient for each bit isapplied to addition circuit 4 by way of line 106, and the remainders areapplied to adder 5 by way of line 105. The output of adder 5 is appliedto second-stage decoder 2 for every bit of the binary number. Decodingfor division by the divisor is performed for each bit by second-stagedecoder 2. Quotients produced by second-stage division are applied toaddition circuit 6 by way of line 109, and the remainders are similarlyapplied to addition circuit 7 by way of line 108. The output of additioncircuit 7 is applied to third-stage decoder 3 for each binary numberbit. Third-stage decoder 3 also performs decoding for division by thedivisor for each bit, and the quotients are applied to addition circuit8 by way of line 112. The remainders for each bit of third-stage decoder3 are applied to corrective decoder 10 by way of line 102. At correctivedecoder 10, corrective output of the quotient is applied to additioncircuit 9 if the sum of the remainder output of each third-stage decoder3 is greater than the divisor and the remainder is outputted as thefinal remainder by way of line 120. If the sum of the remainder ofthird-stage decoder 3 is less than the divisor, the remainder isoutputted without alteration from line 120 as the final remainder. Thequotient output of each decoding stage is outputted from additioncircuits 4, 6, and 8, and the addition result of applying these toaddition circuit 9 along with the corrective value of the quotient fromcorrective decoder 10 is outputted as the final quotient from line 103.

FIG. 8 is a table showing the values of quotient output and remainderoutput of the decoders for each bit of the dividend when the dividend is"1111b" and the divisor is "10b". In the example shown in this decodetable, division can be realized by the one-stage configuration shown inFIG. 3. The quotient "1111b" is obtained by adding at addition circuit 4the quotients "00b", "01b", "10b" and "100b" outputted from each of fourfirst-stage decoders.

If the dividend is "010b", neither quotient output nor remainder outputare outputted for the most significant bit or the second lowest bit. Thequotient "10b" is the sum of the quotient "00b" of the least significantbit and the quotient "10b" of the third lower digit. Similarly, theremainder "01b" is the sum of the quotient "00b" of the leastsignificant bit and the quotient "01b" of the third lowest digit.

Next, regarding an example of the calculation of the two-stageconfiguration of FIG. 4, if the dividend is the 28-bit "FFFFFFFh" andthe divisor is the 3-bit "7h", the quotient output (line 114) offirst-stage addition circuit 4 is "2492489h" and the remainder output(line 107) of addition circuit 5 is "40h". The second-stage division istherefore the division of remainder output "40h" by divisor "7h", thequotient output (line 111) of addition circuit 6 is "9h", no correctivevalue of the quotient is outputted from corrective decoder 10, and theremainder "1h" is obtained. The final quotient, for which this remainder"1h" is the final remainder, i.e., "2492489h"+"9h"="2492492h", isobtained as output (line 103) from addition circuit 9.

Next, regarding an example of calculation by the three-stageconfiguration shown in FIG. 6, if the dividend is the 17-bit "1FFFFh"and the divisor is the 3-bit "7h", the quotient output (line 114) of thefirst-stage addition circuit 4 is "491h", the remainder output (line107) of addition circuit 5 is "26h", the quotient output (line 111) ofsecond-stage addition circuit 6 is "4h", and the remainder output (line110) of addition circuit 7 is "3h". The quotient output (line 113) ofthird-stage addition circuit 8 is "1h", no corrective value of thequotient is outputted from corrective decoder 10, and the remainderoutput "3h". This remainder output "3h" is the final remainder. Thefinal quotient is the sum of the quotient output (line 114) of firststage addition circuit 4, the quotient output (line 111) of second-stageaddition circuit 6, the quotient output (line 113) of third-stageaddition circuit 8, and the corrective value output of the quotient fromcorrective decoder 10, which in this case is"491h"+"4h"+"4h"+"0h"="4924h"

The number of bits of numbers used in computers normally does not exceed64, and an investigation of the number of stages of decoders necessaryfor division using a variety of numbers shows that three stages areclearly sufficient if a corrective decoder is provided in the laststage. For example, if the dividend is of 64 bits, which is the maximum,and a 2-bit number "11b" is chosen as the divisor to maximize the sum ofthe remainders, the maximum value of the sum of remainders in the firststage is the decimal numeral "96", which is a 7-bit number. Similarly,the maximum value of the sum of remainders in the second stage is thedecimal numeral "10", which is a 4-bit number. The maximum value of thesum of remainders in the third stage is the decimal numeral "96", whichis a 7-bit number. Similarly, the maximum value of the sum of remaindersin the second stage is the decimal numeral "10", which is a 4-bitnumber. The maximum value of the sum of remainders in the third stage isthe decimal numeral "6", which is a 4-bit number. In this way, the sumof remainders becomes sufficiently small in three stages, and can bemanaged through correction by decoders.

On this point, as the dividend becomes larger in a constant divisioncircuit that uses a memory according to the prior art, the amount ofmemory required increases radically and the amount of space monopolizedby memory and peripheral memory devices also increases. In contrast, nomore than three stages of decoders are used in this invention and theamount of monopolized space can therefore be reduced.

The timing of the operation of the divider of the present invention willnext be described with reference to FIG. 9. The timing is such that anoperation is completed in the period of one clock regardless of whetherthe divider is of one-stage, two-stage, or three-stage configuration.Here, an example of three-stage configuration will be described.

At the rise of clock 401, the dividend is inputted to the first-stagedecoders from line 101 and the input becomes effective at timing 403.After the delay time resulting from the operation of first-stage decoder1 and addition circuits 4 and 5, output is obtained at lines 114 and 107at timing 404, and the sum of the remainders is applied to second-stagedecoder 2. Next, after the operation delay time of second-stage decoder2 and addition circuits 6 and 7, output is obtained from lines 111 and110 at timing 405 and applied to third-stage decoder 3. Output is nextobtained from lines 112 and 102 after the operation delay time of thirddecoder 3 at timing 406 and applied to addition circuit 8 and correctivedecoder 10. Next, after the operation delay time of addition circuit 8and corrective decoder 10, an output signal is obtained at timing 407 atthe output of addition circuit 8 (line 113) and the output of correctivedecoder 10. The output (line 113) of addition circuit 8 and thecorrective output of the quotient are inputted to addition circuit 9.The remainder output of corrective decoder 10 is outputted at this timeto line 120 as the final remainder. After the operation delay time ataddition circuit 9, the quotient output is obtained at line 103 attiming 408. The next division then becomes possible with the rise of thenext clock 402. In this way, one division can be completed within theperiod of one clock.

Completion of division in the period of one clock in this way not onlyenables high-speed division operations, but greatly simplifies thedesign of clock operation of the circuits of the device overall. As aresult, the present invention is effective in address translation from aone-dimensional address to a two-dimensional address when accessingmemory in, for example, graphics processing.

What is claimed is:
 1. A constant divider comprising:first decodingmeans provided for each bit of inputted dividend data that outputsquotient data and remainder data produced by dividing a value held by abit by a prescribed divisor when said bit is "1"; first quotient addingmeans that adds quotient data outputted for each bit from said firstdecoding means; first remainder adding means that adds remainder dataoutputted for each bit from said first decoding means; second decodingmeans provided for each bit of added remainder data outputted from saidfirst remainder adding means that outputs quotient data and remainderdata produced by dividing a value held by a bit by a prescribed divisorwhen said bit is "1"; second quotient adding means that adds quotientdata outputted for each bit from said second decoding means; correctivedecoding means that outputs a corrective quotient value and a correctedremainder value when a remainder value from remainder data outputted foreach bit from said second decoding means is equal to or greater thansaid prescribed divisor; and third quotient adding means that adds eachoutput of said first quotient adding means, said second quotient addingmeans and said corrective decoding means and outputs final quotientdata.
 2. A constant divider comprising:first decoding means provided foreach bit of inputted dividend data that outputs quotient data andremainder data produced by dividing a value held by a bit by aprescribed divisor when said bit is "1"; first quotient adding meansthat adds quotient data outputted for each bit from said first decodingmeans; first remainder adding means that adds remainder data outputtedfor each bit from said first decoding means; second decoding meansprovided for each bit of added remainder data outputted from said firstremainder adding means that outputs quotient data and remainder dataproduced by dividing a value held by a bit by a prescribed divisor whensaid bit is "1"; second quotient adding means that adds quotient dataoutputted for each bit from said second decoding means; second remainderadding means that adds remainder data outputted for each bit from saidsecond decoding means; third decoding means provided for each bit ofadded remainder data outputted from said second remainder adding meansthat outputs quotient data and remainder data produced by dividing avalue held by a bit by a prescribed divisor when said bit is "1"; thirdquotient adding means that adds quotient data outputted for each bitoutputted from said third decoding means; corrective decoding means thatoutputs a corrective quotient value and a corrected remainder value whena remainder value based on remainder data outputted for each bit fromsaid third decoding means is equal to or greater than said prescribeddivisor; and fourth quotient adding means that adds each output of saidfirst quotient adding means, said second quotient adding means, saidthird quotient adding means, and said corrective decoding means andoutputs final quotient data.
 3. A method of dividing by a constantcomprising the steps of:a first step in which dividend data are inputtedto a first decoding means provided for each bit of said dividend data; afirst decoding step in which quotient data and remainder data aregenerated when each bit of said dividend data is divided by a prescribeddivisor; a first quotient adding step and a first remainder adding stepin which each of quotient data and remainder data generated for each bitin said first decoding step are added and sum data are generated foreach; a second decoding step in which sum data of remainder datagenerated in said first remainder adding step are applied to a seconddecoding means provided for each bit, and in which quotient data andremainder data resulting from dividing each bit of sum data of remainderdata by said prescribed divisor are generated; a second quotient addingstep in which quotient data generated for each bit in said seconddecoding step are added; a corrective decoding step in which, based onremainder data generated for each bit in said second decoding step,quotient corrective data and corrected remainder data are outputted whenthe remainder value is equal to or greater than said prescribed divisor;and an outputting step in which quotient sum data generated in each ofsaid first and second quotient adding steps and said quotient correctivevalue are added and the result is outputted as the final quotient data,and in which the corrected remainder value generated by said correctivedecoding step is outputted as the final remainder data.
 4. A method ofdividing by a constant comprising the steps of:a first step in whichdividend data are inputted to a first decoding means provided for eachbit of said dividend data; a first decoding step in which quotient dataand remainder data are generated when each bit of said dividend data isdivided by a prescribed divisor; a first quotient adding step and afirst remainder adding step in which each of quotient data and remainderdata generated for each bit in said first decoding step are added andsum data are generated for each; a second decoding step in which sumdata of remainder data generated in said first remainder adding step areapplied to a second decoding means provided for each bit, and in whichquotient data and remainder data resulting from dividing each bit of sumdata of remainder data by said prescribed divisor are generated; asecond quotient adding step and a second remainder adding step in whichquotient data and remainder data generated for each bit in said seconddecoding step are each added and sum data for each are generated; athird decoding step in which sum data of remainder data generated insaid second remainder adding step are applied to a third decoding meansprovided for each bit of said sum data of remainder data, and in whichquotient data and remainder data resulting from dividing each bit of sumdata of remainder data by said prescribed divisor are generated; a thirdquotient adding step in which quotient data generated for each bit insaid third decoding step are added; a corrective decoding step in which,based on remainder data generated for each bit in said third decodingstep, quotient corrective data and corrected remainder data areoutputted when the remainder value is equal to or greater than saidprescribed divisor; and an outputting step in which quotient sum datagenerated in each of said first, second, and third quotient adding stepsand said quotient corrective value are added, and the result isoutputted as the final quotient data, and in which the correctedremainder value generated in said corrective decoding step is outputtedas the final remainder data.
 5. A constant divider, which is a dividerin which a dividend is divided by a divisor that is a predeterminednumber, comprising:a decoder group composed of decoders that receive adividend, that are provided for each bit of the binary number of saiddividend, and that, when said bit is "1", output a quotient and aremainder produced by dividing a value held by said bit by the divisor,and when said bit is "0", output "0" as the quotient and the remainder;a quotient adder that adds the value of quotients outputted by eachdecoder of said decoder group; and a remainder adder that adds the valueof remainders outputted by each decoder of said decoder group.
 6. Aconstant divider comprising:a plurality of stages of partial dividersthat divide a dividend by a divisor which is a predetermined number andthat each include: a decoder group composed of decoders that receive adividend, that are provided for each bit of the binary number of saiddividend, and that, when said bit is "1", output a quotient and aremainder produced by dividing a value held by said bit by the divisor;and when said bit is "0", output "0" as the quotient and the remainder;and a quotient adder that adds the values of quotients outputted by eachdecoder of said decoder group; remainder adders in said partial dividersother than the last stage that add values of remainders outputted byeach decoder of said decoder group of that stage; corrective means insaid partial divider of the last stage that outputs a corrected outputof a quotient and a corrected output of a remainder produced by dividingby the divisor the output value of the remainder of each decoder of saiddecoder group of the last stage; and a quotient output adder which addsoutputs of said quotient adders of each stage and said corrected outputof the quotient of the last stage, wherein said partial divider of thefirst stage receives said dividend and said partial dividers of eachsucceeding stage receive as a dividend the output from said remainderadder of said partial divider of the preceding stage; wherein the outputof said quotient output adder is taken as the final quotient and saidcorrected remainder output from said corrective means of said partialdivider of the last stage is taken as the final remainder.
 7. A constantdivider according to claim 6 wherein said corrective means is a decoder.8. A constant divider according to claim 7 wherein the number of saiddecoders included in the first stage of said decoder group of saidplurality of stages of partial dividers is
 64. 9. A constant divideraccording to claim 7 or claim 8 having two stages of said partialdividers.
 10. A constant divider according to claim 7 or claim 8 havingthree stages of partial dividers.
 11. A method of dividing by a constantin which a dividend is divided by a predetermined divisor, said methodbeing a division method which successively executes a plurality ofdivision steps including a decoding step in which a dividend isreceived, and for each bit of the binary number of said dividend, aquotient and remainder produced by dividing a value held by a bit by aprescribed divisor are outputted when said bit is "1", and "0" isoutputted as quotient and remainder when said bit is "0"; and a quotientadding step in which quotients outputted for every bit in said decodingsteps are added;the division method comprising:in said plurality ofdivision steps other than the last division step, remainder adding stepsin which remainders outputted for each bit are added; in the lastdivision step of said plurality of division steps, a corrective step inwhich a corrective output of the quotient and corrective output of theremainder produced by dividing by said prescribed divisor a remainderoutputted for every bit are outputted; and a quotient output adding stepin which, in the first of said division steps, the dividend of thesought division is received as said dividend, and in succeeding of saiddivision steps, the output of said remainder adding step of thepreceding division step is received as said dividend, and moreover, eachoutput of said quotient adding steps and said corrective output of saidquotient of the last of said division steps are added; and whereinoutput of this quotient output adding step is taken as the finalquotient, and the corrected output of said remainder of said correctivestep of the last of said division steps is taken as the final remainder.12. A method of dividing by a constant in which a dividend is divided bya predetermined divisor according to claim 11, wherein said correctivestep is a decoding step using a decoder.
 13. A method of dividing by aconstant in which a dividend is divided by a predetermined divisoraccording to claim 12 wherein said division steps are executed twotimes.
 14. A method of dividing by a constant in which a dividend isdivided by a predetermined divisor according to claim 12 wherein saiddivision steps are executed three times.